1. Field of the Invention
The present invention relates to a method of fabricating a semiconductor device, and more particularly, to a method of fabricating a semiconductor device having a select gate disposed at a side of agate stack layer, where the select gate defined by a spacer has a planar top surface.
2. Description of the Prior Art
A flash memory is a non-volatile memory, which can preserve data within the memory even when an external power supply is turned off. Because a flash memory is re-writable and re-erasable, in recent years it has been widely applied in the fabrication of electrical products, such as mobile phones, digital cameras, video players, personal digital assistants (PDA) or systems on a chip (SOC).
Please refer to FIG. 1, which is a cross sectional diagram illustrating a conventional flash memory cell. As shown in FIG. 1, the flash memory cell 10 includes a semiconductor substrate 12, a gate stack layer 14 disposed on the semiconductor substrate 12, and a select gate 20 disposed at a side of the gate stack layer 14. The gate stack layer 14 includes a floating gate 16 and a control gate 18. The floating gate 16, the control gate 18 and the select gate 20 are commonly made of polysilicon, and the dielectric layers 22/24/26 such as oxide layers are disposed between the gates for electric insulation. The flash memory cell 10 further includes a source region 28 and a drain region 30 disposed in the semiconductor substrate 12 at two sides of the gate stack layer 14. Furthermore, the dielectric layers 22 between the floating gate 16 and the semiconductor substrate 12 may serve as a tunneling oxide, and the hot electrons through the dielectric layers 22 move in or out of the floating gate 16 to enable data accessing.
In the manufacturing process of the conventional flash memory cell 10, the method of forming the select gate 20 may include the following steps. A polysilicon layer (not shown) is conformally deposited on the semiconductor substrate 12, and a blanket etching process is performed to remove a part of the polysilicon layer while the gate stack layer 14 serves as a stop layer. Therefore, the two spacer-shaped select gates can be formed at two sides of the gate stack layer 14. Subsequently, a mask is used to cover one side of the gate stack layer 14, such as the select gate 20 above the drain region 30, and a reactive-ion-etching (RIE) process is performed to remove the select gate at the other side of the gate stack layer 14, such as the select gate (not shown) above the source region 28, to complete the formation of structure of the flash memory cell 10. However, the non-planar top surface of the spacer-shaped select gate 20 may cause unstable landing of a later formed contact plug which is used to connect the select gate 20 and increase the resistance of the flash memory cell 10.
Accordingly, how to provide a select gate having a planar top surface in order to improve the performances of the flash memory cell is still an important issue in the field.